1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a silicon-on-insulator (SOI) device.
2. Description of the Prior Art
SOI wafers are expected to be applicable to semiconductor devices with an ultra-high integration degree, for example, DRAM's of 1 Giga grade or greater. Such SOI wafers consist of an oxide film and a silicon film formed over the oxide film. These SOI wafers provide an ideal insulation among devices fabricated on the silicon film. Accordingly, it is possible to obtain various advantages, for example, prevention of a latch-up phenomenon, a reduced hot electron effect, a reduced short channel effect, etc.
When such SOI wafers are used, it is also possible to greatly reduce the number of steps in the well forming process. This results in a reduction in manufacturing cost.
On the other hand, SOI wafers are mainly fabricated using a bond and etch (BE) method or a separation by implanted oxygen (SIMOX) method. However, these methods are impractical because manufacturing cost is very high.
FIG. 1 illustrates the fabrication of an SOI wafer in accordance with the conventional BE method. In accordance with this method, two sheets of wafers 1 and 2 are first bonded together, as shown in FIG. 1. Thereafter, either wafer 1 or 2 (the wafer 2 in the illustrated case) is ground using processes of grinding-selective etching-polishing in such a manner that its silicon portion on which desired devices will be formed has a thickness a of about 0.1 .mu.m after being ground.
As a result, the wafer, which is ground, is almost wasted. Furthermore, only one SOI wafer is fabricated every fabrication time in accordance with the BE method. Consequently, there is a problem in that the fabrication of SOI wafers is very inefficient.
Moreover, this method does not use the interface 3 with a perfect atomic bonding, but uses the interface 4 with an imperfect atomic bonding. As a result, there is a problem in that the reliance in the fabrication of semiconductor devices is degraded.
Meanwhile, bulk metal oxide semiconductor field effect transistors (MOSFET's) typically have a 4-terminal structure consisting of a gate, a source, a drain and a silicon substrate. However, MOSFET's with an SOI structure does not require connection of contacts and associated wiring to the silicon substrate, as differently from the bulk MOSFET's. Accordingly, MOSFET's with an SOI structure can have a compact chip size.
In the fabrication of CMOS devices, it is unnecessary to form wells. In this case, neighboring active regions of MOSFET's are insulated from one another. Accordingly, it is possible to prevent occurrence of a latch-up phenomenon.
In the case of an SOI device fabricated on a silicon thin film having a small thickness, its source/drain junction is formed throughout the thickness of the silicon thin film. The source/drain has little area junction capacitance. In this case, only a perimeter junction capacitance exists.
In this regard, SOI devices exhibit high-speed low-power consumption characteristics, as compared to bulk MOSFET's.
Now, an example of a conventional technique will be described in conjunction with FIG. 2.
FIG. 2 is a sectional view illustrating an SOI device fabricated in accordance with a conventional method.
In accordance with this method, a first silicon substrate 11 is prepared first, and a silicon oxide film 12 is formed over the first silicon substrate 11. A second silicon substrate 13 having a mesa shape is then formed on the silicon oxide film 12.
Thereafter, a pad oxide film (not shown) and a nitride film (not shown) are sequentially formed over the second silicon substrate 13. The nitride film and pad oxide film are then etched using an etch mask for exposing a portion of the second silicon substrate 13 corresponding to an element isolation region, thereby forming a nitride film pattern and a pad oxide film pattern.
The exposed surface portion of the second silicon substrate 13 is then oxidized, thereby forming a field oxide film 14 on the second silicon substrate 13.
Subsequently, the nitride film and pad oxide film pattern are sequentially removed using an etch process.
Thereafter, a gate oxide film 15 and a polysilicon layer are sequentially formed over the second silicon substrate 13. The polysilicon layer is then patterned to form a gate electrode 16.
Using the gate electrode 16 as a mask, impurity ions are then implanted in a high concentration in the second silicon substrate 13, thereby forming impurity regions 17.
An oxide film (not shown) is then formed over the entire upper surface of the resulting structure. The oxide film is then etched, thereby forming oxide film spacers 18 on side walls of the gate electrode 16.
Subsequently, an insulating film 19 is formed over the resulting structure. Using an etch mask for forming a contact hole, the insulating film 19 is etched until the gate electrode 16 and second silicon substrate 13 are exposed, thereby forming a contact hole (not shown).
Finally, a metal pattern 20 is formed on the exposed surface of the insulating film 19 provided with the contact hole in such a manner that it is buried in the contact hole.
However, the MOSFET having the above-mentioned SOI structure has various problems because the silicon thin film has a very small thickness and because no contact is formed on the semiconductor substrate.
For example, the thickness of the silicon thin film serves as a factor varying the threshold voltage of the MOSFET.
This characteristic will be described in detail. The threshold voltage of the MOSFET can be expressed as follows: EQU V.sub.T =V.sub.FB +Q.sub.B /C.sub.OX
where, V.sub.T represents threshold voltage, V.sub.FB represents flat band voltage, Q.sub.B represents bulk charge, and C.sub.OX represents capacitance of the oxide film.
Referring to the above equation, it can be found that the amount of charge in the channel varies depending on the thickness of the silicon thin film. The threshold voltage of the MOSFET with the SOI structure decreases as the thickness of the silicon thin film is reduced. Accordingly, a variation in thickness of the silicon thin film directly influences the threshold voltage of the MOSFET with the SOI structure.
The thickness range of the silicon thin film adjustable by recently developed techniques is 100 .ANG.. This range may result in a variation in threshold voltage corresponding to about 0.1 Volt in the case of a MOSFET with an SOI structure.
On the other hand, the MOSFET with the above-mentioned SOI structure is also problematic in that there is no path for absorbing minority carriers generated when flowing charges in the saturated channel strike against molecules of silicon grains. This is because the semiconductor substrate is not provided with any contact. As a result, carriers flow into the source/drain via the field region, thereby generating a kink effect resulting in an increase in drain current.
Such a kink effect limits designing of circuits using a MOSFET with an SOI structure. Minority carriers generated in the channel region may be accumulated in the semiconductor substrate unless they are rapidly recombined. In this case, the bias of the semiconductor substrate increases. As a result, the threshold voltage of the MOSFET with the SOI structure is lowered.
The two factors mentioned above are regarded as the most significant problems associated with the use of SOI devices as a semiconductor device for the next generation.
On the other hand, FIG. 3 is a sectional view illustrating an SOI MOSFET fabricated in accordance with a conventional mesa etch method.
In accordance with this method, a first silicon substrate 21 is first prepared, and a silicon oxide film 22 is then formed over the first semiconductor substrate 21. A second silicon substrate 23 having a mesa shape is then formed on the silicon oxide film 22.
A pad oxide film (not shown) is then formed over the second silicon substrate 23. The pad oxide film is then etched using an etch mask for exposing a portion of the second silicon substrate 23 corresponding to an element isolation region, thereby forming a pad oxide film pattern. Using the pad oxide film pattern as an etch barrier, the second silicon substrate 23 is then etched.
Thereafter, a gate oxide film and a polysilicon layer are sequentially formed over the second silicon substrate 23. The polysilicon layer and gate oxide film are then sequentially patterned to form a gate oxide film pattern 24 and a gate electrode pattern 25.
Using the gate electrode pattern 25 and the gate oxide film pattern 24 as a mask, impurity ions are then implanted in a high concentration in the second silicon substrate 23, thereby forming impurity regions 26.
An oxide film (not shown) is then formed over the entire upper surface of the resulting structure. The oxide film is then etched, thereby forming oxide film spacers 27 on side walls of the gate electrode pattern 25.
Subsequently, an insulating film 28 is formed over the resulting structure. Using an etch mask for forming a contact hole, the insulating film 28 is etched until the gate electrode pattern 25 and second silicon substrate 23 are exposed, thereby forming a contact hole (not shown).
Finally, a metal pattern 29 is formed on the exposed surface of the insulating film 28 provided with the contact hole in such a manner that it is buried in the contact hole.
However, the method of FIG. 3 still has the problem involved in the fabrication of the SOI device shown in FIG. 2. Furthermore, the silicon substrate etched in the form of a mesa has the (111)-orientation at its etched surface, thereby varying the threshold voltage of the SOI MOSFET. As a result, a kink phenomenon occurs because two threshold voltages exist in the subthreshold region of the MOSFET.
The above-mentioned conventional methods for fabricating SOI devices have the following problems.
In the case of the method shown in FIG. 1, one of the wafers bonded together is almost wasted. Furthermore, only one SOI wafer is fabricated every fabrication time. Consequently, there is a problem in that the fabrication of SOI wafers is very inefficient.
Moreover, this method uses the interface with an imperfect atomic bonding. As a result, there is a problem in that the reliance in the fabrication of semiconductor devices is degraded.
On the other hand, the conventional methods shown in FIGS. 2 and 3 involve occurrence of a kink phenomenon because it is difficult to control threshold voltage due to a variation in thickness of the silicon substrate. As a result, there is a degradation in the characteristics of semiconductor devices fabricated in accordance with the methods of FIGS. 2 and 3.